137
XMEGA A [MANUAL]
8077I–AVR–11/2012
The I/O pins support synchronous and asynchronous input sensing. Synchronous sensing requires the presence of the
peripheral clock, while asynchronous sensing does not require any clock.
Figure 13-9. Input sensing
Full asynchronous sensing
Figure 13-10. Input sensing
Limited asynchronous sensing
13.6
Port Interrupt
Each port has two interrupt vectors, and it is configurable which pins on the port will trigger each interrupt. Port interrupts
must be enabled before they can be used. Which sense configurations can be used to generate interrupts is dependent
on whether synchronous or asynchronous input sensing is available for the selected pin.
For synchronous sensing, all sense configurations can be used to generate interrupts. For edge detection, the changed
pin value must be sampled once by the peripheral clock for an interrupt request to be generated. See Table 13-1.
For asynchronous sensing which used in all sleep modes except from idle, only port pin 2 on each port has full
asynchronous sense support. This means that for edge detection, pin 2 will detect and latch any edge and it will always
trigger an interrupt request. The other port pins have limited asynchronous sense support. See Table 13-2. This means
that for edge detection, the changed value must be held until the device wakes up and a clock is present. If the pin value
returns to its initial value before the end of the device wake-up time, the device will still wake up, but no interrupt request
will be generated. See Table 13-3.
A low level can always be detected by all pins, regardless of a peripheral clock being present or not. If a pin is configured
for low-level sensing, the interrupt will trigger as long as the pin is held low. In active mode, the low level must be held
until the completion of the currently executing instruction for an interrupt to be generated. In all sleep modes, the low level
Event
Pn
D
Q
R
D
Q
R
Synchronizer
EDGE
DETECT
Synchronous sensing
EDGE
DETECT
Full asynchronous sensing
D
Q
R
D
Q
R
Synchronizer
Wake
IRQ
Inverted I/O
Event
Pn
D
Q
R
D
Q
R
Synchronizer
EDGE
DETECT
Synchronous sensing
EDGE
DETECT
Limited asynchronous sensing
Wake
IRQ
Inverted I/O
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